1. Field of the Invention
The invention relates to the field of cache controllers and cache memories, particularly for microprocessors.
2. Prior Art
The cache controller and cache memory of the present invention is intended for use with the Intel 386.TM. microprocessor, although the invention described may be used with other processing units. Intel Corporation manufactures the Part No. 82385, a high performance 32-bit cache controller for use with the Intel 386.TM.. This part is used in conjunction with a 32 Kbyte cache memory. Many of the signals used in the Intel 82385 and some of the circuitry of this prior art controller are incorporated in the controller of the present invention. A description of the Intel 82385 can be found in "Microprocessor and Peripheral Handbook, Vol. 1 Microprocessor", published by Intel Corporation beginning at page 4-287.
With the Intel 82385 as well as other prior art cache controllers, the controller provides an interface between a microprocessor's local bus and a system bus. The controller also communicates with the cache memory. The controller typically includes the local bus interface, system bus interface, cache directory and cache control circuitry. An ordinary static memory is often used for the cache memory.
The present invention is a departure from the Intel 82385 in that the cache controller and cache memory are fabricated on a single chip. Moreover, one, two or four of these chips may be used as part of a cache army. The chips themselves are able to determine how many other members are in this array and each chip determines its relative position in the array.
The prior art discloses numerous computer systems where circuits may be added into the system with the system recognizing the additional circuits and adjusting for them. For example, microprocessor systems are made with "bit-slice" circuits allowing several of the circuits to be coupled together to provide a microprocessor of a desired width (e.g., 4-bit, 8-bit microprocessor, etc.). Memory is frequently added to a computer system with the system adapting to the additional memory. In some cases, a microprocessor writes and reads into different address locations in order to determine how much memory is present on a bus. In other cases, the memory modules contain information concerning its resources.
As will be seen, the present invention provides a unique method and apparatus for configuring a cache army. The information concerning how many cache memories there are in the array and the relative position of each is distributed among the cache memories and, in effect, is transparent to the overall system. Each of the cache memories is identical, thus there is no need to preprogram or otherwise identify a memory before it is placed in the array.